1 High-Level Design Methodology Overview. - 1. 1 ASIC Design Flow Using Synthesis. - 1. 2 Design Compiler Basics. - 1. 3 Classic Scenarios. - 2 VHDL/Verilog Coding for Synthesis. - 2. 1 General HDL Coding Issues. - 2. 2 VHDL vs. Verilog: The Language Issue. - 2. 3 Finite State Machines. - 2. 4 HDL Coding Examples. - 2. 5 Classic Scenarios 65. - 3 Pre and Post-Synthesis Simulation. - 3. 1 RTL Simulation. - 3. 2 File Text IO in VHDL Using the TEXTIO Package. - 3. 3 VHDL Gate Level Simulation. - 3. 4 Verilog Gate Level Simulation. - 3. 5 Classic Scenarios. - 4 Constraining and Optimizing Designs I. - 4. 1 Synthesis Background. - 4. 2 Clock Specification for Synthesis. - 4. 3 Design Compiler Timing Reports. - 4. 4 Commonly Used Design Compiler Commands. - 4. 5 Strategies for Compiling Designs. - 4. 6 Typical Scenarios When Optimizing Designs. - 4. 7 Guidelines for Logic Synthesis. - 4. 8 Classic Scenarios. - 5 Constraining and Optimizing Designs II. - 5. 1 Finite State Machine (FSM) Synthesis. - 5. 2 Fixing Min Delay Violations. - 5. 3 Technology Translation. - 5. 4 Translating Designs with Black-Box Cells. - 5. 5 Pad Synthesis. - 5. 6 Classic Scenarios. - 6 Links to Layout. - 6. 1 Motivation for Links to Layout. - 6. 2 Floorplanning. - 6. 3 Link to Layout Flow Using FloorPlan Manager. - 6. 4 Basic Links to Layout Commands. - 6. 5 Creating Wire Load Models After Back-Annotation. - 6. 6 Re-Optimizing Designs After P&R. - 6. 7 Classic Scenarios. - 7 FPGA Synthesis. - 7. 1 FPGAs vs. ASICs. - 7. 2 Xilinx 4000 Architecture. - 7. 3 Synopsys Setup (. synopsys_dc. setup) For Xilinx. - 7. 4 Synopsys FPGA Compiler Flow. - 8 Design for Testability. - 8. 1 Introduction to Test Synthesis. - 8. 2 Test Synthesis Using Test Compiler. - 8. 3 Design-Specific Issues in Test Synthesis. - 8. 4 Clock Skew. - 8. 5 Test Compiler Default Test Protocol. - 8. 6 Test Compiler Tips. - 8. 7Examples Showing the Entire Test Synthesis Flow. - 8. 8 Classic Scenarios. - 9 Interfacing Between CAD Tools. - 9. 1 Electronic Data Interchange Format (EDIF). - 9. 2 Forward and Back-annotation. - 9. 3 Design Compiler Input/Output Formats. - 9. 4 Classic Scenarios. - 10 Design Re-use Using Design Ware. - 10. 1 DesignWare Libraries. - 10. 2 Inferring Complex Cells. - 10. 3 Creating Your Own Design Ware Library. - 10. 4 Classic Scenarios. - 11 Behavioral Synthesis An Introduction. - 11. 1 Logic Synthesis. - 11. 2 Behavioral Synthesis Concepts. - 11. 3 Synopsys Behavioral Compiler. - 11. 4 Behavioral Synthesis Design Flow. - 11. 5 Example Using Behavioral Compiler. - 11. 6 Behavioral Compiler Reports. - 11. 7 Is Behavioral Synthesis Right For You?. - 11. 8 Classic Scenarios. - Appendix A. - Sample dc_shell Scripts. - Sample Synopsys Technology Library. - Sample Synopsys Technology RAM Library Model. Language: English